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Layout Engineer #2100002I

PEAK Technical Staffing USA

This is a Full-time position in San Jose, CA posted June 8, 2021.

Posted: 02/18/2021 Employment Type: Direct Placement Category: Semiconductor Processors Job Number: 88546

Job Description

PEAK is looking for a Layout Engineer for a client in San Jose, CA.

This is a full time, direct position with our client.

Local candidates only.
Responsibilities: SRAM memory compiler layout (bit cell, pitch cell, IO & logic).

Signals and Power buses planning.

Hook up from leaf cell to top level & floor planning.

Memory layout is a plus.

Requirements: Education: Associates (AA) or equivalent of 5 years direct memory experience with hands-on layout methodology and tools, Cadence, Caliber verification (DRC, LVS, Antenna, etc.).

Recent Bachelor graduates (who has done internship or project) Experience in advance technology (N10, N7) layout preferred.

Strong interpersonal and communication skills.

Highly organized and detailed oriented.

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