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Design verification engineer

Nytec

This is a Full-time position in San Francisco, CA posted October 31, 2019.

Design Verification EngineerWe are looking for SoC Design Verification Engineer (CW) to provide design verification services for multi CPU/DSP SoC.
● Testbench development System Verilog UVM and C tests
● Integration/development of C tests/APIs and SW build flow
● Integration/development of UVM mailboxes and HW/SW communication components
● Integration of lower-level UVM test benches
● Test plan development
● Power-Aware testbench development and simulations
● Seamless porting between simulation/emulation/prototyping platforms
● Regression set up and debug for RTL/Gate Level Netlist/UPF PA sim/Emulation/Proto
● Coverage collection and closure
● Working with cross-functional teams (DV/Arch/Design/FW) to identify coverage scopeSkillsMinimum :
● 10+ years of experience in RTL Design and Verification area of which 4+ years of experience in SoC Design Verification and HW/SW verification
● Knowledge of System Verilog UVM and vertical testbench integration
● Knowledge of low-level HW/SW interaction and debug
● Knowledge of multi CPU and debug architectures
● Experience with the development of fully automated flowsPreferred Qualification:
● Experience with low-level SW debug disasm, Tarmac, trace
● Experience with RISC-V architecture
● Experience with coresight architecture
● Experience with embedded SW low-level concepts and debug Tarmac, ROM, RAM, linkers, elf, disasm, code sections, cache, security
● Experience with coverage merging across simulation and emulation
● Experience with Power-Aware and Gate Level Netlist in Emulation
● Experience with the development of fully automated flows
● Experience with Gate Level Simulations
● Python scripting