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Substrate Design Engineer

ASICSOFT

This is a Full-time position in San Jose, CA posted April 22, 2020.

TITLE Substrate Design Engineer LOCATION San Jose, CA DURATION 6 months ROLE This position involves the design and layout of new substrates and packaging for next generation biometric sensors.

Candidate will be working closely with the silicon design teams as well as systems teams to design and then lay out new substrates for new ICs.

EXPERIENCE 10 Years experience Deep Cadence toolset knowledge Assembly and requirements experience Experience with Substrate design and layout Wirebond experience Experience with Flip Chip, Wafer Level Fan Out, SiP(System in Package), etc Understanding of design rules for packaging materials, spacing, etc Understanding of impedance Strong experience at the COMPONENT level Some knowledge of low power, high speed design Some EE design experience is desired